1. Field of the Invention
The present application relates to the field of electronics, and more particularly, to methods of forming electronic component structures.
2. Description of the Related Art
To allow backside contact to an electronic component such as an integrated circuit die, electrically conductive through vias are formed in the electronic component. The through vias extend entirely through the electronic component from the active surface to the inactive surface of electronic component.
The inactive surface of the electronic component is etched to reveal through via nubs, i.e., portions, of the through vias. A chemical vapor deposition (CVD) inorganic dielectric layer such as a plasma enhanced chemical vapor deposition (PECVD) silicon oxide is deposited on the inactive surface of the electronic component and completely encloses the through via nubs. Unfortunately, formation of a CVD inorganic dielectric layer is relatively expensive thus increasing the fabrication cost.
The inorganic dielectric layer is thinned using chemical mechanical polish (CMP) to reveal the ends of the through via nubs. More particularly, the inorganic dielectric layer and a portion of the through via nubs are thinned such that the exposed ends of the through via nubs are parallel to and coplanar with the exterior surface of the inorganic dielectric layer. Unfortunately, chemical mechanical polish is relatively expensive thus increasing the fabrication cost.